Digital-to-Analog Converters (DACs) are commonly employed in state-of-the art network communication paths to convert base-band and intermediate-frequency (IF) data from the digital to analog domains. With the ever-increasing data transmission rates and bandwidths in network communication technologies, high-speed, high-precision DACs have become more and more important for achieving desired performances of a wide range of components in a network system. However, it has been challenging to develop DACs that can satisfy the requirements of high frequency systems, such as the 112 GHz systems.
FIG. 1 illustrates an example of a conventional DAC 100 in accordance with the prior art. A single DAC 100 is configured to operate in the full desired Digital-to-Analog (D/A) conversion rate and covert the digital input 101 (e.g., 8 bits digital data) to an analog output 103. As shown in diagram 110, the clock signal 102 to the DAC 100 has the same frequency as the desired data conversion rate (fs). For each digital input 101, a full clock cycle T (=1/fs) is needed for the DAC 100 to accomplish D/A conversion. However, it is difficult to implement such a DAC to high speeds (e.g., 112 GHz) due to the fundamental limitations of the particular technology nodes, e.g., 28 nm, 16 nm, and 7 nm, etc.
One way to scale up DAC speed is to interleave lower speed sub-DACs to add up to a high speed data output. FIG. 2 illustrates an example of a conventional interleaved DAC 200 in accordance with the prior art. In this example, for obtaining an overall data conversion rate fs of 112 GHz, the interleaved DAC 200 includes 4 parallel sub-DACs 211-214, each sub-DAC having a clock (CLK) frequency of 28 GHz (=fs/4). As shown in diagram 220, the clock signal of a respective sub-DAC is shifted by a clock phase of 90° from that of the preceding sub-DAC. The analog outputs 221-224 of the sub-DACs 211 are combined to produce a resultant analog output 231, e.g., they are simply connected together.
To provide the analog outputs from the 4 sub-DACs 211-214 separately and successively in the resultant analog output 231, the clock for each sub-DAC does not have the ON pulse overlap with the ON pulse of the remaining sub-DACs' clocks. Thus, at any given point in time, only one sub-DAC drives the output at 231. As shown in the clock timing diagrams 220, the pulse width of each clock (CLK1-CLK4) extends only for a T= 1/112 GHz, and the analog output of the sub-DAC drops to zero at the end of T, the so-called “return-to-zero” technique. Unfortunately, the difficulties in accomplishing a conversion by a sub-DAC in such a narrow pulse width do not ease up the implementation of individual sub-DACs even if 10 or 100 more interleaved sub-DACs are used.